A high-resolution multibit ΣΔ ADC with digital correction and relaxed amplifier requirements

Author

Sarhang-Nejad, Mohammad ; Temes, Gabor C.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

28

Issue

6

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

648

Lastpage

660

Abstract

A second-order multibit ΣΔ (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2-μm CMOS process. The excellent measured linearity and high S/(N+D) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture

Keywords

CMOS integrated circuits; analogue-digital conversion; delta modulation; error correction; 2 micron; 5.25 MHz; CMOS process; MOSIS p-well; correlated-double-sampling; digital correction; fully differential integrator; high-resolution; multibit sigma-delta ADC; op amp; oversampling ratio; second-order modulator; Calibration; Circuits; Delay; Delta-sigma modulation; Linearity; Resistors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.217979

Filename

217979