A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle

Author

Han, Sung-Rung ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

39

Issue

3

fYear

2004

fDate

3/1/2004 12:00:00 AM

Firstpage

463

Lastpage

468

Abstract

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-μm CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.

Keywords

CMOS integrated circuits; PWM power convertors; timing circuits; voltage-frequency convertors; 500 MHz to 1.25 GHz; CMOS technology; circuit verification; fast-locking pulsewidth control loop; output clock; presettable duty cycle; switched charge pump circuits; voltage-difference-to-digital converter; CMOS technology; Charge pumps; Clocks; DRAM chips; Jitter; Pulse width modulation converters; Space vector pulse width modulation; Switching circuits; Switching converters; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.822781

Filename

1269922