Title :
ESp: Placement by simulated evolution
Author :
Kling, R.M. ; Banerjee, Prithviraj
Author_Institution :
Comput. Syst. Group, Illinois Univ., Urbana, IL, USA
fDate :
3/1/1989 12:00:00 AM
Abstract :
ESP (evolution-based standard cell placement) is a program package designed to perform standard cell placement including macro-block placement capabilities. It uses the novel heuristic method of simulating an evolutionary process to minimize the cell interconnection wire length. While achieving comparable results to popular simulated annealing algorithms, ESP usually requires less CPU time. A concurrent version designed to run on a network of loosely coupled processors, such as workstations connected via Ethernet, has also been developed. For medium to large circuits (>250 cells per processor) concurrent ESP achieves linear speedup
Keywords :
cellular arrays; circuit layout CAD; engineering workstations; local area networks; CPU time; ESP; Ethernet; cell interconnection wire length; concurrent version; evolution-based standard cell placement; heuristic method; linear speedup; macro-block placement capabilities; workstations; Central Processing Unit; Circuit simulation; Coupling circuits; Electrostatic precipitators; Ethernet networks; Integrated circuit interconnections; Packaging; Simulated annealing; Wire; Workstations;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on