• DocumentCode
    911309
  • Title

    ESp: Placement by simulated evolution

  • Author

    Kling, R.M. ; Banerjee, Prithviraj

  • Author_Institution
    Comput. Syst. Group, Illinois Univ., Urbana, IL, USA
  • Volume
    8
  • Issue
    3
  • fYear
    1989
  • fDate
    3/1/1989 12:00:00 AM
  • Firstpage
    245
  • Lastpage
    256
  • Abstract
    ESP (evolution-based standard cell placement) is a program package designed to perform standard cell placement including macro-block placement capabilities. It uses the novel heuristic method of simulating an evolutionary process to minimize the cell interconnection wire length. While achieving comparable results to popular simulated annealing algorithms, ESP usually requires less CPU time. A concurrent version designed to run on a network of loosely coupled processors, such as workstations connected via Ethernet, has also been developed. For medium to large circuits (>250 cells per processor) concurrent ESP achieves linear speedup
  • Keywords
    cellular arrays; circuit layout CAD; engineering workstations; local area networks; CPU time; ESP; Ethernet; cell interconnection wire length; concurrent version; evolution-based standard cell placement; heuristic method; linear speedup; macro-block placement capabilities; workstations; Central Processing Unit; Circuit simulation; Coupling circuits; Electrostatic precipitators; Ethernet networks; Integrated circuit interconnections; Packaging; Simulated annealing; Wire; Workstations;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.21844
  • Filename
    21844