DocumentCode
911351
Title
On the performance/complexity tradeoff in block turbo decoder design
Author
Chi, Zhipei ; Song, Leilei ; Parhi, Keshab K.
Author_Institution
Marvell Semicond. Inc., Sunnyvale, CA, USA
Volume
52
Issue
2
fYear
2004
Firstpage
173
Lastpage
175
Abstract
In this letter, tradeoffs between very large scale integration implementation complexity and performance of block turbo decoders are explored. We address low-complexity design strategies on choosing the scaling factor of the log extrinsic information and on reducing the number of hard-decision decodings during a Chase search.
Keywords
block codes; computational complexity; forward error correction; iterative decoding; turbo codes; Chase search; VLSI; block turbo decoders; complexity tradeoff; forward error correction; hard-decision decoding; integration implementation complexity; iterative decoding; log extrinsic information; low-complexity design strategies; performance tradeoff; AWGN; Additive white noise; Bit error rate; Block codes; Convolutional codes; Forward error correction; Iterative algorithms; Iterative decoding; Optical fiber networks; Turbo codes;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/TCOMM.2003.822728
Filename
1269959
Link To Document