A Parallel Processing Approach for Logic Module Placement

A parallel processing algorithm for logic module placement is presented. Conventionally, such placement problems have been solved on a single processor in a sequential manner. In this paper, it is shown that a two-dimensional processor array structure can be applied to the placement problem, resulting in a substantial reduction of the processing time. This parallel processing algorithm is based on the concept that the adjacent pairwise exchange method could be expanded to the parallel processing case. By using simulation programs, it is shown that the placement results obtained by the parallel processing algorithm are a little better than those obtained by the sequential algorithm. In addition, the theoretical estimations in respect to the processing cycle iterations correspond well with the simulation results.