An Approach to Topological Pin Assignment

One of the methods of increasing routability of an integrated circuit or printed circuit board, is to improve the assignment of connection nets to component (gate, chip, etc.) pins. The quality of a pin assignment is judged based on factors such as predicted wire length, wiring crossovers, and wiring congestion. This paper describes topological heuristic algorithms for pin assignment. Two stages, initial pin assignment and assignment improvement, are described in detail. For all cases, example diagrams are provided. The heuristic approaches demonstrated are highly tunable to specific routers.