Title :
Predicting Transient Upset in Gate Arrays
Author :
Woodruff, Richard L. ; Nelson, Donald A. ; Scherr, Steven
Author_Institution :
United Technologies Microelectronics Center 1575 Garden of the Gods Road Colorado Springs, Colorado 80907
Abstract :
A simulation program for predicting dose rate upset has been adapted from the Power Analysis for Integrated Circuits program (PANIC). The program provides detailed analysis on the Vcc-Vss difference at any location within the array as well as the amount of photocurrent being collected, as a function of design. The simulation has been compared to experiment for a specific design and was found to correlate to within 20% at 5 volts.
Keywords :
Analytical models; CMOS logic circuits; Circuit analysis; Circuit simulation; Circuit testing; Current density; Frequency; Logic arrays; Power dissipation; Rails;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.1987.4337492
