DocumentCode
913049
Title
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
Author
Maly, Wojciech
Author_Institution
Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA, USA
Volume
4
Issue
3
fYear
1985
fDate
7/1/1985 12:00:00 AM
Firstpage
166
Lastpage
177
Abstract
In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.
Keywords
Application specific integrated circuits; Design automation; Design optimization; Integrated circuit modeling; Lithography; Pulp manufacturing; Semiconductor device modeling; Solid modeling; Very large scale integration; Virtual manufacturing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.1985.1270112
Filename
1270112
Link To Document