Title :
FAUST: An MOS Fault Simulator with Timing Information
Author :
Shih, Hsi-Ching ; Rahmeh, Joseph T. ; Abraham, Jocob A.
Author_Institution :
Department of Electrical and Computer Engineering and the Coordinated Science Laboratory, University of Illinois, Urbana, IL, USA
fDate :
10/1/1986 12:00:00 AM
Abstract :
This paper describes FAUST, an MOS fault simulator with timing information. FAUST simulates the effects of realistic physical failures on MOS circuits and uses a static concurrent fault-simulation technique to evaluate the fault-free circuit and all the faulty circuits in one pass. FAUST produces voltage waveforms as well as logic tables with delay information for the fault-free circuit and for each of the faulty circuits.
Keywords :
Analytical models; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Fault detection; Logic circuits; Timing; Voltage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1986.1270226
