DocumentCode :
915529
Title :
MIS: A Multiple-Level Logic Optimization System
Author :
Brayton, Robert K. ; Rudell, Richard ; Sangiovanni-Vincentelli, Alberto ; Wang, Albert R.
Author_Institution :
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA
Volume :
6
Issue :
6
fYear :
1987
fDate :
11/1/1987 12:00:00 AM
Firstpage :
1062
Lastpage :
1081
Abstract :
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don´t-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.
Keywords :
Multiple-level logic; decomposition; don´t cares; extraction; factorization; global phase assignment; kernels; logic minimization; resubstitution; simplification; CMOS logic circuits; CMOS technology; Equations; Logic arrays; Logic circuits; Logic design; Macrocell networks; Minimization; Programmable logic arrays; Timing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1987.1270347
Filename :
1270347
Link To Document :
بازگشت