Analysis of reliability and power efficiency in cascode class-E PAs

Author

Mazzanti, Andrea ; Larcher, Luca ; Brama, Riccardo ; Svelto, Francesco

Author_Institution

Universita di Modena & Reggio Emilia, Italy

Volume

41

Issue

5

fYear

2006

fDate

5/1/2006 12:00:00 AM

Firstpage

1222

Lastpage

1229

Abstract

Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single device, improving long-term reliability. In this paper, we focus on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13-μm CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4-2 GHz.

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF power amplifiers; integrated circuit reliability; 0.13 micron; 1.4 to 2.0 GHz; 1.7 GHz; CMOS power amplifier; cascode class-E power amplifier; cascode-based topologies; device stacking; power efficiency; radiofrequency circuits; switching amplifier; wireless communications; Bandwidth; CMOS technology; Circuit topology; Design optimization; Frequency; Power amplifiers; Prototypes; Stacking; Stress; Voltage; CMOS power amplifier; Class-E; radio-frequency (RF) circuits; switching amplifier; wireless communications;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.872734

Filename

1624411