Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology

Author

Xingsheng Wang ; Binjie Cheng ; Kuang, Jente B. ; Nassif, Sani ; Brown, Andrew R. ; Millar, Campbell ; Asenov, Asen

Author_Institution

Device Modelling Group, Univ. of Glasgow, Glasgow, UK

Volume

30

Issue

6

fYear

2013

fDate

Dec. 2013

Firstpage

18

Lastpage

28

Abstract

This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered.

Keywords

CMOS memory circuits; MOSFET; SRAM chips; elemental semiconductors; integrated circuit design; integrated circuit reliability; negative bias temperature instability; silicon-on-insulator; statistical analysis; 6T-SRAM cell design; NBTI; PBTI; SOI FinFET CMOS SRAM codesign technique; SOI FinFET technology; fi-edge roughness; gate-edge roughness; metal-gate granularity; random interface trapped charges; reliability impact; size 14 nm; statistical variability source random discrete dopant; Aging; Equipment; FinFETs; Integrated circuit modeling; Logic gates; Noise measurement; SRAM; Stability analysis; Statistical analysis; SRAM; co-design; finFET; half select disturb; reliability; stability; static noise margin; variability;

fLanguage

English

Journal_Title

Design & Test, IEEE

Publisher

ieee

ISSN

2168-2356

Type

jour

DOI

10.1109/MDAT.2013.2266395

Filename

6525375