DocumentCode :
918976
Title :
Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
Author :
Chen, Shih-Hung ; Ker, Ming-Dou
Volume :
56
Issue :
7
fYear :
2009
fDate :
7/1/2009 12:00:00 AM
Firstpage :
1466
Lastpage :
1472
Abstract :
MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; semiconductor device breakdown; semiconductor device models; thyristors; MOS-triggered SCR structure; breakdown current; deep-submicrometer CMOS technology; embedded MOS transistor; on-chip ESD protection; on-chip electrostatic discharge; silicon-controlled rectifier device; Breakdown voltage; CMOS process; CMOS technology; Circuits; Electrostatic discharge; MOSFETs; Protection; Rectifiers; Robustness; Thyristors; ESD protection; Electrostatic discharge (ESD); silicon-controlled rectifiers (SCRs);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2009.2021359
Filename :
4982724
Link To Document :
بازگشت