Rule checking at the register level

For huge, complex circuits, checking design rules at a level of abstraction above the gate level can identify architectural problems early on. Today´s more mature equivalence checkers require little user input, but are not able to verify the quality or correctness of an original design. By adding RTL-DRC capability to formal verification tools, they can be used to find and correct RTL design problems early in the design cycle, with little or no extra effort necessary on the part of the designer