DocumentCode :
923782
Title :
A compact MOST model for design analysis
Author :
Kalinowski, J.J.
Volume :
60
Issue :
8
fYear :
1972
Firstpage :
1000
Lastpage :
1001
Abstract :
A dc model of the 4-terminal MOS transistor is described that eliminates the need for piecewise definition of the channel current while maintaining sufficient physical correspondence to accurately represent modern MOS devices used in arrays. The determination of model parameters is straightforward.
Keywords :
Circuit analysis; Closed-form solution; Equations; MOS devices; MOSFETs; Modems; NASA; Numerical stability; Steady-state; Voltage;
fLanguage :
English
Journal_Title :
Proceedings of the IEEE
Publisher :
ieee
ISSN :
0018-9219
Type :
jour
DOI :
10.1109/PROC.1972.8829
Filename :
1450759
Link To Document :
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