Logic design using digital summation threshold-logic gates

The advent of IC technology has resulted in the fabrication of IC threshold gates which are competitive, both in performance and cost with standard logic packages. Of them, the multioutput digital summation threshold-logic (DSTL) gate is considered to be a potential candidate of future interest. In this paper, an algorithm has been developed to realise nonthreshold functions utilising the multioutput capability of DSTL gates. In this context, optimal realisation has been discussed. An universal logic module (ULM) has been proposed, based on DSTL approach, and an optimised structure of ULM for 4-variable functions is suggested.