An approach to sequential circuit construction in LSI programmable arrays

Programmable logic arrays (PLAs) are nowadays extensively used in the design of combinational and sequential logic circuits for LSI/VLSI implementation of digital systems. A PLA realisation that requires lesser number of cells for implementing the required logic results in a reduced chip area, and this is suitable for LSI/VLSI designs. The PLA design technique for sequential logic circuits, presented in the paper, is motivated by the above consideration of reduced number of cells. The proposed method takes advantage of the common next-state table entries to reduce the number of P-terms required, thereby reducing the number of PLA cells. The method is formalised by an iterative construction procedure which produces the PLA fuse tables, together with the corresponding state codings. A Pascal program implementing this procedure has been developed.