Analytical study of punchthrough in buried channel P-MOSFETs

The punchthrough phenomenon in buried-channel (BC) P-MOSFETs (p-metal oxide-semiconductor field effect transistors) depletion-mode devices is investigated analytically using the voltage-doping transformation (VDT) technique. The resulting punchthrough current model shows a high degree of accuracy over a wide range of biases and channel lengths while still retaining the simplicity required for CAD (computer-aided-design) models. The mean error over about 300 experimental current-voltage points is as small as 3%. The mechanism of punchthrough in a BC-P-MOSFET is shown to be due to the DIBL (drain-induced barrier lowering) effect, which is further shown to be considerably enhanced by two effects. These effects, a surface inversion layer screening (SILS) and a drain-induced channel enlargement (DICE), are deduced and investigated analytically. The methods leading to a suppression of these effects are shown. Owing to its accuracy and generality, the present punchthrough analysis is expected to find applications in design and process optimization as well as in the simulation of advanced BC-P-MOSFETs