Title :
An advanced single-level polysilicon submicrometer BiCMOS technology
Author :
Brassington, Michaelk P. ; El-Diwany, Monir H. ; Razouk, Reda R. ; Thomas, Michael E. ; Tuntasood, Prateep T.
Author_Institution :
Fairchild Res. Center, Palo Alto, CA, USA
fDate :
4/1/1989 12:00:00 AM
Abstract :
An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (fT=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized
Keywords :
BIMOS integrated circuits; VLSI; integrated logic circuits; LDD; MOS gates; MOS transistors; NMOS; PMOS; Si; advanced VLSI; base/collector; circuit integration; high-speed logic circuits; lightly doped extrinsic base; nonselective CVD; planarized metal interconnect scheme; power consumption; source/drain regions; submicrometer BiCMOS technology; vertical n-p-n transistors; vertical-walled contacts; vias; BiCMOS integrated circuits; Energy consumption; Integrated circuit interconnections; Logic circuits; MOS devices; MOSFETs; Planarization; Silicon; Transistors; Very large scale integration;
Journal_Title :
Electron Devices, IEEE Transactions on
