Title :
Efficient testing of optimal time adders
Author_Institution :
Angewandte Math. und Inf., Univ. des Saarlandes, Saarbrucken, West Germany
fDate :
9/1/1988 12:00:00 AM
Abstract :
Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log2(n)-4 and 6 log2(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of basic cells). The results are considered pertinent to establishing the correct behavior of a given VLSI chip
Keywords :
VLSI; adders; integrated logic circuits; logic testing; VLSI chip; carry look-ahead adder; conditional sum adder; optimal time adders; Adders; Circuit faults; Circuit testing; Digital arithmetic; Electrical fault detection; Fault detection; Logic arrays; Logic testing; Tree data structures; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
