Title :
Part 2: An optimising analysis of hierarchical multipliers for VLSI
Author :
Yung, H.C. ; Allen, C.R.
Author_Institution :
University of Newcastle upon Tyne, Department of Electrical & Electronic Engineering, Merz Laboratories, Newcastle upon Tyne, UK
fDate :
4/1/1984 12:00:00 AM
Abstract :
An analysis of area-time complexity is presented for a specific hierarchical-multiplier design. The analysis is generally applicable to a variety of multiplier designs having hierarchical structure and may be used as a basic analytical tool for other arithmetic structures with hierarchy. Area and time performance are derived in terms of branching ratio, and it is found the optimal area-time complexity is obtained for a branching ratio of four.
Keywords :
digital integrated circuits; large scale integration; multiplying circuits; optimisation; VLSI; area performance; area-time complexity; arithmetic structures; branching ratio; hierarchical multipliers; optimising analysis; time performance;
Journal_Title :
Electronic Circuits and Systems, IEE Proceedings G
DOI :
10.1049/ip-g-1:19840012
