Title :
Modelling interconnect yield in reconfigurable circuits
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
Reconfigurable interconnect is required to implement defect-tolerant circuits. The impact of this wiring on yield is usually either ignored or overstated. A method is presented that allows the determination of the yield impact of the interconnect in reconfigurable circuits through the expanded use of critical area parameters.
Keywords :
VLSI; circuit reliability; failure analysis; integrated circuit technology; redundancy; semiconductor device models; VLSI; critical area parameters; defect-tolerant circuits; interconnect faults; interconnect yield modelling; reconfigurable circuits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19890821
