Impact of stress-induced backflow on full-chip electromigration risk assessment

Author

Haznedar, Haldun ; Gall, Martin ; Zolotov, Vladimir ; Ku, Pon Sung ; Oh, Chanhee ; Panda, Rajendran

Author_Institution

Freescale Semicond. Inc., Austin, TX

Volume

25

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1038

Lastpage

1046

Abstract

This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficient implementation in computer-aided design (CAD) tools for designing high-performance microprocessor chips involving large databases. Derived from a well-known hydrostatic stress model in tree interconnects (J. Appl. Phys., vol. 47, no. 4, p. 1203, 1976; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, p. 576, 1999; Microelectron. Reliab., vol. 39, no. 11, p. 1667, 1999), the system is readily modified for evaluating EM risk in mesh topologies. The authors demonstrated a significant increase in the predicted lifetime of a high-performance microprocessor with the application of the proposed method to filter out risk-free structures from subsequent statistical EM risk calculations

Keywords

circuit CAD; electromigration; integrated circuit interconnections; integrated circuit reliability; logic design; microprocessor chips; network topology; stress analysis; CAD tools; computer-aided design; full-chip electromigration risk assessment; hydrostatic stress model; integrated circuit reliability; linear system formulation; mass displacements; mesh topologies; metal ions; microprocessor chips; stress gradients; stress-induced backflow; tree interconnects; wire segments; wiring topologies; Design automation; Electromigration; Equations; Linear systems; Microprocessor chips; Risk management; Stress; Topology; Wire; Wiring; Electromigration; integrated circuit reliability;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2005.855941

Filename

1629138