Compact modeling of on-chip ESD protection devices using Verilog-A

Author

Li, Junjun ; Joshi, Sopan ; Barnes, Ryan ; Rosenbaum, Elyse

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois, Urbana, IL

Volume

25

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1047

Lastpage

1063

Abstract

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions

Keywords

MOSFET; electrostatic discharge; resistors; semiconductor device models; semiconductor diodes; NMOS transistor; Verilog-A; alternating current simulation; behavioral language; circuit-level simulation; device ON-resistance; diode; electrostatic discharge; large-signal models; on-chip ESD protection devices; resistor; self-heating model; small-signal models; transient high-current conditions; transient simulation; vertical n-p-n transistor; Circuit simulation; Electric breakdown; Electrostatic discharge; Hardware design languages; Integrated circuit reliability; MOSFETs; Protection; Resistors; SPICE; Semiconductor diodes; Electrostatic discharge (ESD); Verilog-A; metal–oxide–semiconductor (MOS) model; reliability;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2005.855948

Filename

1629139