DocumentCode
928823
Title
New techniques for untestable fault identification in sequential circuits
Author
Syal, Manan ; Hsiao, Michael S.
Author_Institution
Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA
Volume
25
Issue
6
fYear
2006
fDate
6/1/2006 12:00:00 AM
Firstpage
1117
Lastpage
1131
Abstract
This paper presents two low-cost fault-independent techniques that can be used to identify significantly more untestable faults than could be identified by earlier fault-independent techniques. A new theorem and an efficient implementation of the theorem for the purpose of identifying sequentially untestable faults are presented first. Unlike the single-fault theorem where the stuck-at fault is injected exclusively in the last time frame of the k-frame unrolled circuit, this theorem enables a fault injection in any time frame within the unrolled sequential circuit. To efficiently apply the authors\´ concept to untestable fault identification, sequential implications are used to extend the unobservability propagation of gates to multiple time frames during single-line conflict analysis. Then, a new technique called "maximizing local impossibilities" is proposed. This technique efficiently identifies multiple-node conflicting assignments by analyzing logical relationships local to Boolean gates in the circuit. Using this new concept in conjunction with a powerful implication engine enables identification of many more untestable faults that were missed by the single-line conflict-based approach. Since this approach concentrates on identifying conflicting combinations locally around each Boolean gate in the circuit, its complexity is linear in the size of the circuit. The application of these two proposed techniques to the International Symposium on Circuits and Systems (ISCAS) 1985 and ISCAS 1989 Sequential Benchmark Circuits showed a significant increase in the number of faults identified as untestable, at practically no overhead in both the memory and the execution time
Keywords
automatic test pattern generation; fault location; sequential circuits; ATPG; Boolean gate; automatic test pattern generator; fault injection; local multinode conflicts; maximizing local impossibilities; multiple-node conflicting assignments; sequential circuits; sequential implications; single-line conflict analysis; untestable fault identification; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Sequential analysis; Sequential circuits; Test pattern generators; Automatic test pattern generator (ATPG); local multinode conflicts; sequential implications; untestable faults;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2005.855967
Filename
1629144
Link To Document