DocumentCode :
929226
Title :
Design Verification and Testing of the WE 32100 CPUs
Author :
Wadsack, Ronald L.
Author_Institution :
AT&T Bell Laboratories
Volume :
1
Issue :
3
fYear :
1984
Firstpage :
66
Lastpage :
75
Abstract :
This article reviews the design verification and testing methods that evolved during the development of four AT&T 32-bit microprocessors. Software modeling and regression testing??without hardware breadboards??proved to be a viable approach for these high-performance CPU chips. AT&T investigated five built-in testability features: a compressed-data output pin, macro-ROM internal access, register/PLA internal access, self-test macro-ROM code, and a board-level tri-state feature. Internal probing in a bench-top facility was more efficient than software-based, internal access-oriented debugging, and fault simulations were performed to confirm the design, layout, and physical tests.
Keywords :
Access protocols; Acoustic testing; CMOS technology; Circuit testing; Logic gates; Logic testing; Semiconductor device modeling; Software testing;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.1984.5005653
Filename :
5005653
Link To Document :
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