Fundamental Timing Problems in Testing MOS VLSI on Modern ATE

Most manufacturers of VLSI test equipment are designing 256-pin test heads with transmission lines leading from the device under test to driver-comparator circuits that are sometimes 50 cm away. While this is acceptable for testing ECL circuits whose outputs are designed to drive 50-ohm loads, serious problems arise with MOS devices designed to drive capacitive loads. Unless timing measurements are made at the 50-percent level of the initial voltage step at the comparators and theoretical corrections are applied, MOS measurements can be in error by as much as 10 ns even though modern automatic test equipment can be adjusted to subnanosecond accuracy. The author points out that there is an urgent need for manufacturers to develop more compact test heads if silicon and gallium arsenide very high speed ICs are to be properly tested.