DocumentCode
930680
Title
CAVLC Encoder Design for Real-Time Mobile Video Applications
Author
Rahman, Choudhury A. ; Badawy, Wael
Author_Institution
Calgary Univ., Calgary
Volume
54
Issue
10
fYear
2007
Firstpage
873
Lastpage
877
Abstract
This brief presents a new context-based adaptive variable length coding (CAVLC) architecture. The prototype is designed for the H.264/AVC baseline profile entropy coder. The proposed design offers area savings by reducing the size of the statistic buffer. The arithmetic table elimination technique further reduces the area. The split VLC tables simplify the process of bit-stream generation and also help in reducing some area. The proposed architecture is implemented on Xilinx Virtex II field-programmable gate array (2v3000fg676-4). Simulation result shows that the architecture is capable of processing common/quarter-common intermediate format frame sequences in real-time at a core speed of 50 MHz with 6.85-K logic gates.
Keywords
VLSI; digital arithmetic; field programmable gate arrays; logic design; mobile communication; video coding; CAVLC encoder design; H.264/AVC baseline profile entropy coder; Xilinx Virtex II; arithmetic table elimination; bit-stream generation; context-based adaptive variable length coding architecture; field-programmable gate array; frequency 50 MHz; logic gate; real-time VLSI architecture; real-time mobile video application; statistic buffer; Arithmetic; Automatic voltage control; Entropy coding; Hardware; Logic gates; Prototypes; Statistics; Table lookup; Video coding; Video compression; Context-based adaptive variable length coding (CAVLC); H264/AVC; entropy coding; hardware encoder; real-time VLSI architecture;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2007.902215
Filename
4349237
Link To Document