High-k gate dielectrics with ultra-low leakage current for sub-45nm CMOS

The results of a new method of high-kappa dielectric formation are reported. For effective oxide thickness of 0.39 nm, the leakage current density of metal-high-kappa-silicon structure is about 1 times 10^-12 A/cm² for gate voltage from +3 to -3 V. The descriptive statistics and process variation data presented demonstrate that the process is robust and manufacturing tools can be developed without any fundamental barrier.