Title :
A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits
Author :
Layman, Paul A. ; Chamberlain, Savvas G.
Author_Institution :
Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
Abstract :
A compact VLSI MOSFET model that includes an integrated thermal noise model and a methodology for the analysis of the effects of thermal noise on the performance and error rates of digital integrated circuits is presented. The usefulness of the model and methodology is demonstrated by comparing simulation results for signal-to-noise ratio to analytic results for the balanced bit-line architecture of the single-device DRAM and the associated cross-coupled pair sense amplifier. The design options and tradeoffs related to thermal noise are introduced for both the balanced bit lines and the sense amplifier are considered. The error rate as a function of signal-to-noise ratio is determined, and possible limits to DRAM construction due to inherent thermal noise are highlighted.<>
Keywords :
VLSI; circuit CAD; electron device noise; field effect integrated circuits; insulated gate field effect transistors; integrated circuit technology; integrated memory circuits; random-access storage; semiconductor device models; MOS VLSI digital circuits; SNR; VLSI MOSFET model; analytic results; associated cross-coupled pair sense amplifier; balanced bit-line architecture; compact thermal noise model; design options; design tradeoffs; effects of thermal noise; error rates of digital integrated circuits; inherent thermal noise; integrated thermal noise model; limits to DRAM construction; methodology; performance; signal-to-noise ratio; simulation results; single-device DRAM; soft error rates; Analytical models; Digital integrated circuits; Error analysis; Integrated circuit modeling; Integrated circuit noise; MOSFET circuits; Performance analysis; Random access memory; Signal to noise ratio; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
