Syndrome-testable logic design using DSTL arrays for detecting stuck-at and bridging faults

Fault-detection problems in combinational networks design with a novel logic block consisting of a cellular interconnection of AND/OR gates, called DSTL gates (digital summation threshold logic), are considered in the paper. Techniques have been proposed for making these structures easily syndrome testable in order to detect all single stuck-at faults, all bridging faults between any two lines and also for detecting a large number of multiple stuck-at and bridging faults.