Bus-Invert Coding for Low Noise, Low Power 2eSST VME64x Block Transfers

The VME64x standard defines a double edge source synchronous block transfer (2eSST) capable to sustain a data transfer rate up to 320 MByte/s on the VMEbus. This level of performance is achieved by double edge clocking a 64-bit bus with bursts of data strobe pulses. The switching activity of such a wide bus on a shared backplane challenges the signal integrity and the data transfer reliability. The Bus-invert is a well known coding technique developed to lower the peak power dissipation in I/O busses by decreasing their switching activity. It has been originally proposed for lowering the power consumption of CMOS VLSI devices and so reducing the on-chip line coupling and noise. In this paper we discuss how the Bus-Invert coding can be applied to improve the 2eSST performance. A custom designed board-set has been used to characterize jitter, noise and power consumption with different data patterns, coding schemes and bus loading conditions. The hardware overheads introduced by the encoding algorithm is discussed in the view of deployments in low-latency, real-time applications.