DocumentCode
9343
Title
Time-Interleaved 
Modulators for FPGAs
Author
Podsiadlik, Tomasz ; Farrell, Ronan
Author_Institution
Benetel Ltd., Dublin, Ireland
Volume
61
Issue
10
fYear
2014
fDate
Oct. 2014
Firstpage
808
Lastpage
812
Abstract
This brief describes and analyzes a technique of increasing a sampling rate in a sigma-delta (ΣΔ) modulator based on a discrete-time description, which is an extension of existing techniques of parallelization. The limitations in the signalto-noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of a low-pass ΣΔ modulator characterized by a short critical path is used in this brief to validate the technique. An implementation of a modulator shows the increase in the sampling rate from 100 to 400 MHz.
Keywords
delta-sigma modulation; field programmable gate arrays; modulators; sampling methods; FPGA; digital system; discrete-time description; field programmable gate array; parallelization. techniques; sampling rate; short critical path; sigma-delta modulator; signal-to-noise ratio; time-interleaved low-pass ΣΔ modulator; Clocks; Equations; Frequency modulation; Hardware; Signal to noise ratio; Time-domain analysis; Sampling frequency; sigma??delta $(SigmaDelta)$; time interleaved (TI);
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2014.2345293
Filename
6870470
Link To Document