Abstract :
The RISC approach to computer design is described. The use of pipelining, a characteristic feature of RISC computers, is discussed. The simple instruction encoding, memory instructions, and optimizing compilers are examined. Implementation, performance, potential disadvantages, and future trends are considered
Keywords :
pipeline processing; reduced instruction set computing; RISC; computer design; instruction encoding; memory instructions; optimizing compilers; performance; pipelining; reduced instruction set computers; Assembly; CMOS technology; Computer aided instruction; Computer architecture; Hardware; High level languages; Operating systems; Program processors; Reduced instruction set computing; Very large scale integration;
