Design of a Master Device for the Multifunction Vehicle Bus

This paper presents the design of a network master device for the multifunction vehicle bus. An analysis of the specifications for this bus administrator reveals that the functional design can be arranged in 14 operational blocks and in a special memory for communication data known as the traffic store. System-on-a-chip strategies have been adopted in order to cope with this great complexity. The architecture includes a standard on-chip bus, which is aimed at interconnecting all the modules as cores attached to it by an established interface. In this way, creation flow can be concurrent, and design for reuse is made easier. The entire architecture has been coded in SystemC not only for verification purposes but also for setting the intermediate point in the refinement process toward the register transfer-level design. After validating this executable description by simulation, the hardware/software partition has been performed following the codesign philosophy. Estimations about consumed silicon area, hardware response time, occupied program memory, and software execution time have been made in order to calculate a cost function for each functional block: the cost-performance difference. From these, an optimum hardware/software architecture has been obtained. As a result, the electronic platform for the master device has been generated on a field-programmable gate array. The final implementation contains a soft processor as the main component, a ROM, a RAM, some internal registers, and the Traffic Store.