DocumentCode :
939960
Title :
Architecture and synthesis for on-chip multicycle communication
Author :
Cong, Jason ; Fan, Yiping ; Han, Guoling ; Yang, Xun ; Zhang, Zhiru
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Volume :
23
Issue :
4
fYear :
2004
fDate :
4/1/2004 12:00:00 AM
Firstpage :
550
Lastpage :
564
Abstract :
For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a cluster of computational elements, local registers, and a local controller. On top of the RDR microarchitecture, novel layout-driven architectural synthesis algorithms have been developed for multicycle communication, including scheduling-driven placement, placement-driven simultaneous scheduling with rebinding, and distributed control generation, etc. The experimentation on a number of real-life examples demonstrates promising results. For data flow intensive examples, we obtain a 44% improvement on average in terms of the clock period and a 37% improvement on average in terms of the final latency, over the traditional flow. For designs with control flow, our approach achieves a 28% clock-period reduction and a 23% latency reduction on average.
Keywords :
VLSI; circuit layout CAD; convergence; multichip modules; network topology; trees (mathematics); wiring; ClockTune; Pentium IV PC; buffer insertion-sizing algorithm; clock distribution; delay minimization; delay-power tradeoffs; industrial clock tree; minimum delay-power zero skew buffer insertion-sizing; multichip architecture; multichip synthesis; on-chip multicycle communication; polynomial time; power minimization; routing; timing-design convergence; very large scale integration designs; wire-sizing algorithm; wire-sizing problems; Clocks; Clustering algorithms; Communication system control; Computer science; Delay effects; Design methodology; Microarchitecture; Processor scheduling; Registers; Wires;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2004.825872
Filename :
1278532
Link To Document :
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