Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V_T) stability performance. At small gate stress voltages (0≤V_ST≤15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V_T(ΔV_T) compared to the ΔV_T in the absence of a drain bias. The measured shift in V_T appears to agree with the defect pool model that the ΔV_T is proportional to the number of induced carriers in the a-Si:H channel.