A 27-mW 3.6-gb/s I/O transceiver

Author

Wong, Koon-Lun Jackie ; Hatamkhani, Hamid ; Mansuri, Mozhgan ; Yang, Chih-Kong Ken

Author_Institution

Univ. of California, Los Angeles, CA, USA

Volume

39

Issue

4

fYear

2004

fDate

4/1/2004 12:00:00 AM

Firstpage

602

Lastpage

612

Abstract

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm² in a 0.18-μm 1.8-V CMOS technology.

Keywords

CMOS integrated circuits; comparators (circuits); impedance matching; phase control; phase locked loops; synchronisation; timing circuits; transceivers; 0.18 micron; 1.8 V; 27 mW; 3.6 Gbit/s; CMOS technology; I/O transceiver; channel equalization; charge pump; chip-to-chip applications; impedance matching; offset compensation; phase control; sampling bandwidth control; signal integrity; timing recovery circuit; voltage-mode transmitter; Bandwidth; CMOS technology; Charge pumps; Circuits; Impedance matching; Sampling methods; Timing; Transceivers; Transmitters; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.825259

Filename

1278578