DocumentCode :
949038
Title :
Improving the yield of deep submicron CMOS processes by controlling the grain size of poly-Si gate through post deposition rapid thermal anneal
Author :
Kamal, Abu H M
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Volume :
15
Issue :
4
fYear :
2002
fDate :
11/1/2002 12:00:00 AM
Firstpage :
552
Lastpage :
554
Abstract :
The morphology of gate poly-Si was found to be critical for achieving fully functional 4-Mb SRAM dies with 0.18-μm complementary metal-oxide-semiconductor (CMOS) process. Although the functionality of 4-Mb SRAM had been achieved with as-deposited poly-Si gate, it is highly likely that the surface roughness of the as-deposited poly-Si is a major concern for sub-0.18-μm technology. In this report, it is shown that the small-size grains, achieved by recrystallizing as-deposited amorphous Si via rapid thermal anneal prior to gate patterning, is very effective in reducing the number of failing bits of 4-Mb SRAM dies. The conventional deposition process for gate poly-Si can therefore be adopted for fabricating sub-0.18-μm CMOS integrated circuits.
Keywords :
CMOS memory circuits; SRAM chips; grain size; integrated circuit yield; rapid thermal annealing; surface topography; 0.18 micron; 4 Mbit; SRAM dies; Si; deep submicron CMOS processes; failing bits; grain size; poly-Si gate; post deposition rapid thermal anneal; small-size grains; surface roughness; yield; CMOS process; Grain size; Morphology; Process control; Random access memory; Rapid thermal annealing; Rapid thermal processing; Rough surfaces; Size control; Surface roughness;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2002.804904
Filename :
1134173
Link To Document :
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