DocumentCode :
949675
Title :
A systolic realization of symmetric block matching algorithm for HD-MAC system
Author :
Kim, Sang-Yeon ; Lee, Jung-Hee ; Kim, Seong-Dae ; Jang, Kue-Hwan ; Lee, Ki-Bong
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Volume :
39
Issue :
3
fYear :
1993
Firstpage :
277
Lastpage :
284
Abstract :
A method for VLSI realization of a symmetric block matching algorithm (SBMA) with systolic array processors is described. The VLSI implementation of the SBMA has some problems because the blocks in the current frame are matched to the averaged blocks of the corresponding previous and next frames. In order o solve such problems, a new error measure with some advantages in terms of real motion and VLSI implementation is proposed. A VLSI architecture for SBMA with the proposed measure is presented. Using this measure, the SBMA was implemented with existing efficient systolic architectures. The proposed measure showed better performance in terms of real motion and insensitivity to noise than the existing one
Keywords :
VLSI; image processing equipment; motion estimation; systolic arrays; television standards; HD-MAC system; VLSI realization; current frame; motion estimation; symmetric block matching algorithm; systolic array processors; systolic realization; Equations; HDTV; Hardware; Motion estimation; Motion measurement; Recursive estimation; Search methods; Systolic arrays; Very large scale integration; Video codecs;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.234594
Filename :
234594
Link To Document :
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