Single-event upset in commercial silicon-on-insulator PowerPC microprocessors

Author

Irom, F. ; Farmanesh, F.F. ; Johnston, A.H. ; Swift, Gary M. ; Millward, D.G.

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

Volume

49

Issue

6

fYear

2002

fDate

12/1/2002 12:00:00 AM

Firstpage

3148

Lastpage

3155

Abstract

Single-event upset effects from heavy ions and protons are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors, and compared with results for similar devices with bulk substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The upset rates are low enough to allow these devices to be used in space applications where occasional register or functional operating errors can be tolerated.

Keywords

CMOS digital integrated circuits; integrated circuit testing; ion beam effects; microprocessor chips; proton effects; silicon-on-insulator; space vehicle electronics; 64 bit; IBM; Motorola; SOI PowerPC microprocessors; charge collections depth; cross sections; functional operating errors; heavy ions; junction-isolated CMOS; protons; radiation tests; register errors; single-event upset effects; space applications; upset rates; Laboratories; Manufacturing processes; Microprocessors; Propulsion; Protons; Silicon on insulator technology; Single event upset; Substrates; Testing; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2002.805441

Filename

1134274