On the design automation of the memory-based VLSI architectures for FIR filters

An approach to automating the design of memory-based VLSI architectures for FIR (finite impulse response) filters has been developed. The automation is based on the exploration of the design space and schemes for efficient memory replacement, algorithm formulation, architecture design, and evaluation method. Various schemes and design considerations were integrated to produce a parameterized MBA (memory-based architecture) that can easily be tuned to various hardware-speed requirements. This MBA is characterized by three design parameters. Differently configured MBAs result from specifying different values for these parameters. Hardware-speed evaluation formulas were established based on the required elements in MBAs. These elements include ROM, adders, and shift registers. These formulas and a cell library of a target technology can be used to design an optimally configured MBA by searching for the best values of the design parameters with the aid of a computer. Using the evaluation formulas and the parameterized architecture, an area-minimized architecture can be synthesized under a speed specification. Based on these results, an automatic synthesis too has been developed