High-speed operation of a low-power 4-bit serial-to-parallel converter

Author

Vichot, Paul A. ; Grabow, Barry E. ; Piket-May, Melinda

Author_Institution

Appl. Phys. Lab., Johns Hopkins Univ., Laurel, MD, USA

Volume

12

Issue

4

fYear

2002

fDate

12/1/2002 12:00:00 AM

Firstpage

1891

Lastpage

1896

Abstract

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit yield for use as a core element in an address decoder or a demultiplexer. First, the circuit design and optimization are discussed. Simulated performance of the circuit shows proper operation at 20 Gb/s, with a discussion of its potential for use at even higher rates. The power dissipation is computed to be 28 μW in continuous operation and the predicted within-wafer yield is 95%. Measured results are then given for data rates of 100 Mb/s and 1 Gb/s.

Keywords

circuit optimisation; circuit simulation; demultiplexing equipment; high-speed integrated circuits; integrated circuit layout; integrated circuit yield; logic design; low-power electronics; superconducting logic circuits; 1 Gbit/s; 100 Mbit/s; 20 Gbit/s; 28 muW; 4 bit; address decoder; circuit design; circuit optimization; continuous operation; core element; data rate; demultiplexer; design goals; high circuit yield; high-speed operation; latching logic; low-power 4-bit superconducting serial-to-parallel converter; power dissipation; simulated circuit performance; within-wafer yield; Aggregates; CMOS technology; Communication switching; Decoding; Latches; Superconducting logic circuits; Switches; Telecommunication switching; Throughput; Trigger circuits;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2002.806029

Filename

1134292