Fault-tolerant memory organization: Impact on chip yield and system cost

A method is presented for utilizing the loop-to-loop functional independence of multiloop bubble memory devices. The locations of the defective loops are stored in inexpensive flag chips which are located at rows of memory chips. A statistical analysis is presented to determine the number of redundant loops needed on each memory chip to guarantee a given data capacity. A memory System cost reduction of up to 50% is demonstrated for the fault-tolerant scheme chosen as a model.