Author :
Sugibayashi, Tadahiko ; Sakimura, Noboru ; Honda, Takeshi ; Nagahara, Kiyokazu ; Tsuji, Kiyotaka ; Numata, Hideaki ; Miura, Sadahiko ; Shimura, Ken-ichi ; Kato, Yuko ; Saito, Shinsaku ; Fukumoto, Yoshiyuki ; Honjo, Hiroaki ; Suzuki, Tetsuhiro ; Suemitsu,
Abstract :
This paper describes a recently developed 16-Mb toggle magnetic random access memory (MRAM). It has 100-MHz burst modes that are compatible with a pseudo-SRAM even though the toggle cell requires reading and comparing sequences in write modes. To accelerate operating clock frequency, we propose a distributed-driver wide-swing current-mirror scheme, an interleaved and pipelined memory-array group activation scheme, and a noise-insulation switch scheme. These circuit schemes compensate the toggle cell timing overhead in write modes and maintain write-current precision that is essential for the wide operational margin of MRAMs. Because toggle cells are very resistant to write disturbance errors, we designed the 16-Mb MRAM to include a toggle MRAM cell. The MRAM was fabricated with 0.13-mum CMOS and 0.24-mum MRAM processes with five metal layers.
Keywords :
CMOS memory circuits; magnetic storage; random-access storage; CMOS; burst modes; clock frequency; frequency 100 MHz; interleaved memory-array group activation scheme; magnetic random access memory; noise-insulation switch scheme; pipelined memory-array group activation scheme; size 0.13 mum; size 0.24 mum; storage capacity 16 Mbit; toggle MRAM; toggle cell timing overhead; tributed-driver wide-swing current-mirror scheme; write modes; Acceleration; CMOS process; Equivalent circuits; Frequency; Magnetic fields; Magnetic tunneling; Magnetization; Random access memory; Switches; Writing; Burst mode; magnetic random access memory (MRAM); pseudo-SRAM; toggle cell;
