Improved yield models for fault-tolerant memory chips

Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip fault eliminates the need for yield-model formulas. This makes possible the accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. A second improvement results from the use of separate frequency distributions for different failure mechanisms instead of the multivariate distributions used until now. The yields of array islands with their own redundant word and bit lines are combined using a new yield formula. Examples of the use of this technique for dynamic-random-access-memory (DRAM) chips are given. A simplified pragmatic approximation technique that appears to be in good agreement with experimental data is also discussed