• DocumentCode
    955010
  • Title

    Calculation method to obtain worst-case static noise margins of logic circuits

  • Author

    Lohstroh, J.

  • Author_Institution
    Philips Research Laboratories, Eindhoven, Netherlands
  • Volume
    16
  • Issue
    8
  • fYear
    1980
  • Firstpage
    273
  • Lastpage
    274
  • Abstract
    A relatively simple calculation method is introduced using the flip-flop method, and by using the criterion that, with marginal static noise applied to the flip-flop, the loopgain is 1. As an example, the worst-case static series voltage noise margin of I2L is calculated.
  • Keywords
    bipolar transistor circuits; logic design; noise; I2L; calculation method; logic circuits; series voltage noise; worst case static noise margin flip flop method;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19800199
  • Filename
    4243964
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=955010