DocumentCode :
955607
Title :
Screening ICs on the bare chip level: temporary packaging
Author :
Chu, Dahwey ; Reber, Cathleen A. ; Palmer, David W.
Author_Institution :
Sandia Nat. Lab., Albuquerque, NM, USA
Volume :
16
Issue :
4
fYear :
1993
fDate :
6/1/1993 12:00:00 AM
Firstpage :
392
Lastpage :
395
Abstract :
Several different temporary packaging concepts for integrated circuits (ICs) for pretest at speed and burn-in are introduced. Temporary packaging is achieved using standard labor and equipment resources already employed in permanent packaging. Experiments were carried out to validate the pretest process, and results are presented for the various materials used in the pretest process. The preferred method for temporary packaging along with the selected materials used is presented. Temporary packaging of integrated circuits for pretest with reasonable yield is demonstrated as feasible
Keywords :
circuit reliability; integrated circuit testing; packaging; IC screening; bare chip level; burn-in; pretest; temporary packaging; yield; Assembly; Bonding; Copper; Electronics packaging; Integrated circuit packaging; Integrated circuit testing; Microassembly; Multichip modules; Packaging machines; Wire;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/33.237935
Filename :
237935
Link To Document :
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