The Power PC 601 microprocessor

Author

Becker, Michael C. ; Allen, Michael S. ; Moore, Charles R. ; Muhich, John S. ; Tuttle, David P.

Author_Institution

Motorla, Inc., Austin, TX, USA

Volume

13

Issue

5

fYear

1993

Firstpage

54

Lastpage

68

Abstract

The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described. The general-purpose processor contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle. The bus interface and storage control mechanisms can be configured for a wide range of system designs, from low-cost desktop personal computers to high-performance multi-processor systems. The PowerPC architecture, machine organization, chip packaging technology, and performance are discussed.<>

Keywords

microprocessor chips; packaging; 32-Kb cache; Power PC 601 microprocessor; PowerPC architecture; bus interface; chip packaging technology; machine organization; performance; storage control mechanisms; superscalar machine organization; system designs; Clocks; Computer architecture; Control systems; Costs; High performance computing; Microcomputers; Microprocessors; Operating systems; Power system modeling; Reduced instruction set computing;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.238002

Filename

238002