Title :
Sequential faults and aliasing
Author :
Pilarski, Slawomir ; Kameda, Tiko ; Ivanov, Andre
Author_Institution :
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
fDate :
7/1/1993 12:00:00 AM
Abstract :
Aliasing is studied for delay and stuck-open faults. It is shown that, as the test sequence length is increased, the probability of aliasing for such faults tend to 2-k, where k is the number of binary memory elements in a linear compactor. The result is based on the assumption that the linear compactor has an irreducible characteristic polynomial. Some recent results on combinational faults are special cases of the results presented here
Keywords :
fault location; logic testing; sequential circuits; aliasing; binary memory elements; combinational faults; delay; irreducible characteristic polynomial; linear compactor; probability; sequential faults; stuck-open faults; test sequence length; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Delay; Fault detection; Registers; Sequential circuits; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
